Article (6)
Signature of electrothermal transport in 18nm vertical junctionless gate-all-around nanowire field effect transistors Auteur(s): Houssem Rezgui, Yifan Wang, Chhandak Mukherjee, Marina Deng, Cristell Maneux Lien HAL : https://hal.science/hal-04739562v1 3D Logic circuit design oriented electrothermal modeling of vertical junctionless nanowire FETs Auteur(s): Sara Mannaa, Arnaud Poittevin, Cédric Marchand, Damien Deleruyelle, Bastien Deveautour, Alberto Bosio, Ian O’connor, Chhandak Mukherjee, Yifan Wang, Houssem Rezgui, Marina Deng, Cristell Maneux, Jonas Müller, Sylvain Pelloquin, Konstantinos Moustakas, Guilhem Larrieu Lien HAL : https://hal.science/hal-04230911v1 Strategies for Characterization and Parameter Extraction of Vertical Junction-Less Nanowire FETs Dedicated to Design Technology Co-Optimization Auteur(s): Cristell Maneux, Chhandak Mukherjee, Marina Deng, Guilhem Larrieu, Yifang Wang, Bruno Wesling, Houssem Rezgui Lien HAL : https://hal.science/hal-04230924v1 Nanoscale Thermal Transport in Vertical Gateall-around Junction-less Nanowire Transistors-Part II: Multiphysics Simulation Auteur(s): H. Rezgui, Mukherjee Chhandak, Y. Wang, M. Deng, A. Kumar, J. Müller, G. Larrieu, C. Maneux Lien HAL : https://hal.science/hal-04296531v1 Evidence of trapping and electrothermal effects in vertical junctionless nanowire transistors Auteur(s): Y. Wang, Mukherjee Chhandak, H. Rezgui, M. Deng, Jonas Müller, S. Pelloquin, Guilhem Larrieu, C. Maneux Lien HAL : https://hal.science/hal-04297709v1 Nanoscale Thermal Transport in Vertical Gate-All-Around Junctionless Nanowire Transistors—Part I: Experimental Methods Auteur(s): Mukherjee Chhandak, H. Rezgui, Y. Wang, M. Deng, A. Kumar, Jonas Müller, G. Larrieu, C. Maneux Lien HAL : https://hal.science/hal-04296517v1Conference proceedings (4)
FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation Auteur(s): Ian O'Connor, Sara Mannaa, Alberto Bosio, Bastien Deveautour, Damien Deleruyelle, Tetiana Obukhova, Cédric Marchand, Jens Trommer, Cigdem Cakirlar, Bruno Neckel Wesling, Thomas Mikolajick, Oskar Baumgartner, Mischa Thesberg, David Pirker, Christoph Lenz, Zlatan Stanojevic, Markus Karner, Guilhem Larrieu, Sylvain Pelloquin, Konstantinous Moustakas, Jonas Muller, Giovanni Ansaloni, Alireza Amirshahi, David Atienza, Jean-Luc Rouas, Leila Ben Letaifa, Georgeta Bordea, Charles Brazier, Mukherjee Chhandak, Marina Deng, Yifan Wang, Marc Francois, Houssem Rezgui, Reveil Lucas, Cristell Maneux Lien HAL : https://hal.science/hal-04739538v1 Evidence of Trapping and Electrothermal Effects in Vertical Junctionless Nanowire Transistors Auteur(s): Yifang Wang, Houssem Rezgui, Mukherjee Chhandak, Marina Deng, Abhishek Kumar, Jonas Müller, Guilhem Larrieu, Cristell Maneux Lien HAL : https://hal.science/hal-04231605v1 Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design Auteur(s): Yifan Wang, Mukherjee Chhandak, Houssem Rezgui, Marina Deng, Cristell Maneux, Sara Mannaa, Ian O’connor, Jonas Müller, Sylvain Pelloquin, Guilhem Larrieu Lien HAL : https://hal.science/hal-04231616v1 Thermal consideration in nanoscale gate-all-around vertical transistors Auteur(s): Guilhem Larrieu, Houssem Rezgui, Abhishek Kumar, Jonas Müller, Sylvain Pelloquin, Yifan Wang, Marina Deng, Aurélie Lecestre, Cristell Maneux, Mukherjee Chhandak Lien HAL : https://laas.hal.science/hal-04189328v1Send a email to Houssem REZGUI :
