Christophe JEGO

I received the M.S. and Ph.D. degrees from the Université Rennes 1, Rennes, France, in 1996 and 2000, respectively. I joined the Electronic Engineering Department of the graduate engineering school IMT Altantiques, Brest, France, as a full-Time Associate Professor in 2001. I was a visiting professor in the Department of Electrical and Computer Engineering at McGill University, Montreal, Quebec, Canada, during 10 months (Sept. 2006 – June 2007). In 2009, I received Research Habilitation from Université of Bretagne Sud, Lorient, France. Then, I joined the graduate engineering school ENSEIRB-MATMECA, Bordeaux, France, as a full-time Professor in 2010. From 2013 to 2017, I was the Dean of the Electronics department of ENSEIRB-MATMECA Engineering School. From 2017 to 2022, I was the Dean of Studies of ENSEIRB-MATMECA Engineering School. From 2022 to 2024, I was the Dean of Research, Innovation and Technology Transfer of ENSEIRB-MATMECA Engineering School.

I am also member of the CSN research team (3 professors, 3 associate professors, 1 assistant professors, 18 PhD students and 1 engineers) of the CNRS IMS laboratory, UMR 5218. From 2013 to 2019, I was member of IEEE Signal Processing Society Technical Committee on Design and Implementation of Signal Processing Systems (DISPS). I have served as Technical Program Co-Chair of the IEEE Conference on Design and Architectures for Signal and Image Processing (DASIP 2012) and as Co-Chair of the IEEE Conference on Design and Architectures for Signal and Image Processing (DASIP 2013). I have also served on the Program Committees of the IEEE SiPS, EEE ISVLSI, IEEE ISTC, IEEE ICASSP and IEEE GlobalSIP. I was the Guest Co-Editor of Special Issue of Journal of Real-Time Image Processing, 2012, title: Design and Architectures for Real-Time Image Processing in Embedded Systems. I was the Guest Editor in Chief of a Special Issue of EURASIP Journal on Advances in Signal Processing, 2013, title: Design and Architectures for Signal and Image Processing. From 2015 to 2017, I was a member of the electrical and computer engineering evaluation group for the Discovery Grants Evaluation of Natural Sciences and Engineering Research Council of Canada (NSERC). From 2016 to 2019, I was associate editor for IEEE Communications Letter.

My research activities are concerned with Algorithm-Architecture-Matching approach for FEC decoders in digital communications systems. My work is about all aspects of mapping algorithms to architectures to implementations. I am the author or coauthor of 40 peer-reviewed publications in international journals and 114 peer-reviewed articles in international conferences.

Current Ph.D. Students

I am currently co-supervising the following 6 Ph.D. students:

• Afaf ALAOUI MRANI (October 2022 – …) :
  • PhD Title : “Studying the strengths and limitations of reinforcement learning methodsfor polar codes decoding”
  • PhD funding : ANR project entitled AI4CODE

• Diane ORHAN (October 2022 – …) :
  • PhD Title : “Modeling and dynamic optimization of software radio chains on heterogeneous architectures”
  • PhD funding : Specific doctoral contract for a normalien 
    

• Filipe POUGET (February 2023 – …) :
  • PhD Title : “Study and implementation on ASIC of low imprint RISC-V instruction set architectures”
  • PhD funding : CIFRE with STMicroelectronics

• Emmanuelle BODJI (April 2023 – …) :
  • PhD Title : “Optimization of LDPC encoder/decoder with AI”
  • PhD funding : CIFRE with ORANGE Labs

• Alexandre VALADE (October 2023 – …) :
  • PhD Title : “Design of FEC codes for future networks”
  • PhD funding : PEPR project entitled future networks

• Maxime GRAS-CHEVALIER (Jan. 2024 – …) :
  • PhD Title : “RISC-V processor study for automotive : The architecture and its various abstraction layers”
  • PhD funding : CIFRE with STELLANTIS

Former Ph.D. Students

I have co-supervised the following 24 Ph.D. students:

• Erwan PIRIOU (Oct 2003 – Jan 2007) :
  • PhD Title : Design, implementation and prototyping of flexible architectures dedicated to bloc turbo decoding using a system level design flow
  • Current position : Research Engineer at CEA LIST
    

• Irene M. MAHAFENO (Oct 2003 – May 2007) :
  • PhD Title : Study of interleave-division multiple-access (IDMA) systems
  • Current position : Work Package Manager at Thales Alenia Space

• Camille LEROUX (Oct 2005 – Sept 2008) :
  • PhD Title : Architectures for high data rate turbo decoding of product codes
  • Current position : Associate Professor at Enseirb-Matmeca/Bordeaux INP
    

• Haisheng LIU (Oct 2005 – July 2009) : 
  • PhD Title : Energy efficient architecture for turbo decoder
  • Current position : Senior software engineer on embedded system at Trustonic
    

• Daoud KARAKOLAH (Oct 2006 – Nov 2009) : 
  • PhD Title : Design of architectures for iterative MIMO receivers
  • Current position : Associate Professor at ISSAT- Damas
    

• Meng LI (Oct 2008 – Jan 2012) : 
  • PhD Title : Design and integration of Bit-Interleaved Coded Modulations (BICM) receiver architecture
  • Current position : Senior Researcher at IMEC
    

• Quang Trung DONG (Oct 2008 – Dec 2012) :
  • PhD Title : Stochastic decoding process for Turbo Codes
  • Current position : Project Manager at Viettel Semiconductor Technology
    

• Oscar SANCHEZ GONZALEZ (October 2009 – March 2013) : 
  • PhD Title : On the higher efficiency parallel decoder for convolutional turbo codes
  • Current position : Architecte FPGA Engineer at Mipsology
    

• Yang-Yang TANG (January 2010 – January 2013) : 
  • PhD Title : An error control code for transient fault tolerant model of logic circuits
  • Current position : Project manager and Architect expert at Hisilicon
    

• Alain HAROUN (November 2010 – November 2014) :
  • PhD Title : Iterative receivers for MIMO Systems based on belief propagation
  • Current position : Hardware Designer FPGA at Expleo Group
    

• Guillaume BERHAULT (October 2012 – October 2015) :
  • PhD Title : Hardware architecture exploration for the decoding of Polar Codes
  • Current position : Product Manager at Mondial Relay
    

• Thibaud TONNELLIER (November 2013 – July 2017) :
  • PhD Title : Contribution to the improvement of the decoding performance of turbo codes : algorithms and architecture
  • Current position : Digital Electronics and Telecommunications engineer at Airbus Defence and Space
    

• Guillaume DELBERGUE (February 2015 – December 2017) :
  • PhD Title : Advances in SystemC/TLM virtual platforms : configuration, communication and parallelism
  • Current position : DevOps Engineer Freelance at OPSaaS and CEO Hiventive  
    

• Matthieu LEONARDON (October 2015 – Décembre 2018) :
  • PhD Title : Polar decoding on programmable architectures
  • Current position : Associate Professor at IMT Atlantique
    

• Yann DELOMIER (October 2016 – June 2020) :
  • PhD Title : Design and prototyping of error-correcting code decoders from behavioural models
  • Current position : ASIC/SoC Processing Architect Engineer at Thales Alenia Space
    

• Adrien CASSAGNE (October 2017 – December 2020) :
  • PhD Title : Optimization and parallelization methods for software-defined radio
  • Current position : Associate Professor at Sorbonne University 
    

• Vincent PIGNOLY (October 2017 – Jan  2021) :
  • PhD Title : Study of LDPC codes for optical space applications and design of the associated decoders
  • Current position : FPGA/ASIC Design Engineer at Thales Alenia Space
    

• Victor GRIMBLATT (Jan 2018 – October 2021) :
  • PhD Title : Design of an integrated digital circuit for the Internet of Things (IoT) applied to agronomy
  • Current position : Managing Director at Synopsys
    

• Yassine FAIZE (October 2018 – March 2022) :
  • PhD Title : Design of autonomous and intelligent wireless sensors for a sustainable, responsible and highly connected campus
  • Current position : FPGA Engineer at Keysom
    

• Jonathan SAUSSEREAU (Jan 2021 – Jan 2024) :
  • PhD Title : AsteRISC: Flexible RISC-V Processor Architectures and Tools for Design Space Exploration
  • Current position : Assistant Professor at Enseirb-Matmeca/Bordeaux INP

• Denis SHEMONAEV (November 2020 – May 2024) :
  • PhD Title : Definition of an object localization algorithm based on video streams from multiple cameras and evaluation on an MPSoC FPGA
  • Current position :  FPGA Engineer at Keysom

• Malek ELLOUZE (October 2020 – July 2024) :
  • PhD Title : Distance properties of polar codes: theory and applications
  • Current position : R&D manager at Leoblue

• Hugues ALMORIN (October 2020 – November 2024) : 
  • PhD Title : Architectural design space exploration using high-level synthesis: applicability to radar processing systems
  • Current position : Embedded system Enginer at ARELIS

• Ian FISCHER-SCHILLING (October 2021 – March 2025) :
  • PhD Title : Design and FPGA prototyping of advanced recevier based on Expectation Propagation
  • Current position : Linkedin