Conference proceedings (5)
A 860mV and 73.5Ppm/°C Voltage Reference that Relies on Back-Gate Biasing Techniques in 28nm FD-SOI Technology Auteur(s): Maxime Guillot, Yann Deval, Herve Lapuyade, François Rivet Année de publication: 2025 Journal: DOI: 10.1109/icecs61496.2024.10849174 Lien HAL: https://hal.science/hal-04945900v1 A 728mV and 23.4ppm/°C voltage reference using parasitic diode biasing for temperature compensation in 28nm FD-SOI technology Auteur(s): Maxime Guillot, Yann Deval, Herve Lapuyade, Francois Rivet Année de publication: 2025 Journal: DOI: Lien HAL: https://hal.science/hal-05298823v1 The impact of Back-Gate biasing and layout on temperature sensitivity of transistors in FD-SOI CMOS technology Auteur(s): Yann Deval, Maxime Guillot, Herve Lapuyade, Francois Rivet Année de publication: 2025 Journal: DOI: Lien HAL: https://hal.science/hal-05298730v1 Temperature Compensation in FD-SOI Transistors: A Novel Approach with 27% Performance Improvement via Parasitic Diode Biasing Auteur(s): Maxime Guillot, Yann Deval, Herve Lapuyade, Francois Rivet Année de publication: 2024 Journal: DOI: Lien HAL: https://hal.science/hal-04790652v1 A Zero Temperature Coefficient Voltage Reference, Stability and Versatility using 28nm FD-SOI Technology Auteur(s): Maxime Guillot, Yann Deval, Herve Lapuyade, Kawori Sekine, Kazuyuki Wada, Francois Rivet Année de publication: 2023 Journal: DOI: Lien HAL: https://hal.science/hal-04218085v1Send a email to Maxime GUILLOT :
