This thesis pioneers a 60 GHz CMOS receiver architecture designed to replace wired USB 3.2 connections with robust wireless links. Targeting 10 Gb/s with ultra-low latency and a stringent BER (), the work bridges system requirements and silicon implementation. The core innovation is a reconfigurable Low-Noise Amplifier (LNA) featuring a novel ‘zero-coupling’ stacked inductor technique, fabricated and validated in 22 nm FDSOI technology. Combined with a hierarchical system-level validation of the full front-end chain, the study demonstrates the feasibility of a compact (0.14 mm²), high-performance wireless interface, paving the way for seamless cable-free interconnects in next-generation electronics.
