Thesis defense of Anais TOURISSAUD - December 14th, 2023

Anaïs TOURISSAUD will defend her thesis on December 14th, 2023 at 10:00 a.m., (amphi JP. DOM – IMS Laboratory) on the subject : “Design of a front-end with a power amplifier, a VGA and a phase shifter in SiGe technology for 5G applications at millimeter frequencies”.

The introduction of 5G and improved data rates have led to the deployment of new frequency ranges, particularly around 30 GHz, reducing signal range. To address this limitation, beamforming is a solution that involves combining various signal beams using the transmitting antennas at the end of the chain. Digital beamforming involves the use of phase shifters and VGAs (variable gain amplifiers) to precisely control the phase and gain of the signals, enabling the beam to be precisely steered. The main aim of this thesis is to design a digital beamforming system that is both reliable and flexible, while maintaining optimum energy efficiency in 130nm SiGe BiCMOS technology. To this end, three sub-circuits (phase shifter, VGA and PA) are proposed and then assembled to create an RF front-end module capable of meeting 5G requirements, in collaboration with UMS, with the aim of driving a GaN HPA for base station applications.To achieve the best possible performance in a digital beamforming system, it is essential to be able to correct amplitude and phase errors on the antenna array. The proposed phase shifter is of the passive RTPS type, and the VGA is composed of bipolar transistors, guaranteeing exceptional robustness as a function of binary code in relation to input and output impedance. The design of these circuits at millimeter frequencies is complex due to the increased sensitivity of the components to parasitic interference. Component placement and layout play an essential role in the design to ensure proper circuit operation at such high frequencies. The three sub-circuits were carefully dimensioned and designed to optimize their individual performances, while keeping in mind the project objective: to co-design an integrated 130 nm SiGe BiCMOS chip, enabling beam steering (phase shifter), sidelobe reduction (VGA) and signal amplification (PA). It should be noted that a major constraint of this technology lies in the physical phenomenon of the transistors. To remedy this, an avalanche compensation solution has been proposed and explained in this work, through the use of a current mirror, enabling the avalanche to be repelled and thus guaranteeing the correct operation of the chip even at high output power levels.

Contact our team

If you have a request or questions about the laboratory, please contact our team.