In this thesis, we develop accurate compact models for the JL-VNWFETs through extensive static, dynamic and thermal characterizations. We also performed reliability characterization and associated analysis of the underlying degradation mechanisms for implementing a compact model of Negative Bias Temperature Instability in the JL-VNWFETs. The final compact model can then be used for performance prediction of 3D logic circuits under different operating conditions and provide feedback to process engineers through a Design Technology Co-Optimization loop, thus constituting a critical link in the value chain of 3D JL-VNWFET based hardware design.
False-color TEM image of different layers of a single Si nanowire and 3D representation of a passive NOR [1]
Simulations and DC measurements results of Id-Vg and Id -Vd
[1] A. Kumar, J. Müller, S. Pelloquin, A. Lecestre, et G. Larrieu, « Logic Gates Based on 3D Vertical Junctionless Gate-All-Around Transistors with Reliable Multilevel Contact Engineering », Nano Lett., vol. 24, no 26, p. 7825‑7832, juill. 2024, doi: 10.1021/acs.nanolett.3c04180.
