Lucien PAQUIEN will defend his thesis on April 11th, 2024 at 10:00 a.m., (M256 Grenoble INP – Phelma) on the subject : “: A 5G mmW bi-directional integrated transmitter in a hybrid and digital beamforming system”.
The increasing demand for data rate for mobile telecommunications has led to the use of beamforming systems in order to notably limit the impact of free space propagation losses (FSPL) over the link budget, due to the elevation of the operating frequency. In order to be able to direct a directional beam concentrating the majority of the gain of the antenna array towards a given user, a large number of integrated radio frequency front-ends (RFFE) is necessary. Conventionally, 5G RFFEs generally consist of a low noise amplifier (LNA), and a power amplifier (PA). The latter are physically dissociated, and are alternatively addressed using a commuted element, in order to operate in time division duplexing (TDD). In this case, not only does the switched element involve losses and a significant silicon surface requirement, but also the RFFEs are only used half the time (due to TDD). Also, this large silicon area required must then be multiplied by the number of elements that constitutes the beamforming system. In addition, the spacing between each antenna constituting the antenna array being proportional to the wavelength, the latter could therefore reach higher operating frequencies if the RFFEs are miniaturized. In this work, a solution allowing the elimination of the need for a commuted element, as well as the merging of the LNA and PA is proposed, inducing a strong reduction in the silicon surface area required for the same operation that conventional architectures, using the GF 22nm CMOS FD-SOI technology. Although the design of millimeter functions (mmW) will be discussed, the frequency conversion aspect as well as the study of baseband functions will also be covered, including the design of a RF passive mixer, two reconfigurable second- and fourth-order active-RC low-pass filters, a variable gain amplifier (VGA), a 50Ω analog buffer, a double pole double throw (DPDT) switch, as well as a generation chain of quadrature signals, done from the combination of a hybrid coupler (HCPLR), and an external off-chip local oscillator (LO). The complete system will be simulated to demonstrate the relevancy of these structures regarding performances and required silicon surface, and axis for improvement will also be listed.
