In the context of information security, the evolution of internal electrical test techniques and their ability to identify and read sensitive data from memory technologies is a crucial matter, their technological watch is therefore necessary. A few studies have been carried out on the readout of volatile memories such as SRAM and non-volatile memories such as Flash, FeRAM and RRAM. Despite the attractiveness of magneto-resistive memories (MRAM), due to their potential to become a universal memory, a direct readout of data at the core of the MRAM circuit has never been demonstrated in the literature prior to this work.
This work demonstrates that it is possible to retrieve data stored in MRAMs using invasive techniques. This manuscript presents the methodology used to recover stored data (“0” / “1”) in a Toggle MRAM (130 nm technology node) and in a STT-MRAM (40 nm technology node). These components thus represent the two types of MRAM on the market, with current and more advanced technology nodes. The methodology consists of four stages: determination of the most suitable measurement technique, technological analysis to identify the physical structure of the memory, preparation of the memory to make the data accessible, and reading of the data. Two readout attempts are detailed: measurement of the magnetic orientation of magnetic tunnel junctions (known as MTJs, where the information is stored) and measurement of their electrical resistance induced by the magneto-resistance phenomenon, using an atomic force microscope (AFM) and Nanoprobing. The used AFM modes are MFM (magnetic mode), C-AFM (conductive mode) and SSRM (resistive mode). For both memory types, it’s the C-AFM current measurement that makes it possible to discriminate between the two logic states. This is achieved after a complex preparation of the backside of the device, consisting of a chemical opening, a polishing down to the transistors, FIB etches of metallization levels surrounding the MTJ and metal deposition. The advantage of this methodology is that it should be applicable to any technology node and potentially to all resistance-based memories (SOT-MRAM, RRAM and PCM).
