Justin SOBAS will defend his thesis on December 13rd, 2023 at 10:30 am, (amphi JP. DOM – IMS Laboratory) on the subject : “Measure and prediction of latest-generation digital circuits’ reliability under ageing effect”.
In the 2010s, evolution of planar transistor (MOSFET) architecture has led to the extension of design limits, resulting in the FinFET. The FinFET, a transistor with a fin-shaped channel rising out of its surface, is widely used in the latest generation of digital circuits with nodes down to five nanometers. So far, FinFET has proved its high performance, low power consumption and low cost, but what about its reliability? Has the architectural evolution of FinFET allowed digital circuits to be improved at the cost of reduced reliability?
In this thesis, we present the test bench we have developed to age and measure degradation in FPGAs based on 16-nanometre FinFETs. By implementing ring oscillators and measuring the evolution of the oscillation frequency, which depends on the threshold voltage of the transistors, we observe the effect of the failure mechanisms (BTI, HCI and TDDB) at the transistor scale. Our test bench seems to be the most accurate in the state of the art for measuring degradation, giving it the capacity to measure degradation for ageing conditions close to operating conditions, making our observationsmore lifelike.
After 8000 hours of ageing, we have observed the degradations measured in 5103 ring oscillators distributed into nine FPGAs. We present a method to distinguish degradations in logic resources from degradations in routing resources. We model degradation and failure as a function of temperature, voltage, stress duty cycle and the resources used in the FPGA. Finally, we compare our degradation measured in a 16 nm FinFET FPGA with a 28 nm MOSFET FPGA in order to show the evolution of reliability between MOSFET and FinFET in FPGAs.
If you have a request or questions about the laboratory, please contact our team.