Thesis defense of Jonathan SAUSSEREAU - January 8th, 2024

Jonathan SAUSSEREAU will defend his thesis on January 8th, 2024 at 10:15 a.m., (amphi JP. DOM – IMS Laboratory) on the subject : “AsteRISC : Flexible RISC-V architectures and tools for design space exploration”.

In the electronic industry, designers are often faced with the challenge of evolving requirements throughout the development lifecycle and post-deployment of products. This challenge is compounded by the lengthy timespan from ASIC design to manufacturing and the inherent inflexibility of digital architectures once etched onto silicon. Thus, approaches allowing modification after manufacturing are attractive solutions.
However, such flexibility typically incurs additional costs in resource utilization, performance overhead, and power consumption. To address this, designers must strike an optimal balance among these competing factors, crafting an architecture that minimizes extra costs while meeting the specific demands of the specifications.
The research explores a processor-based solution as a viable alternative to the fixed one. The proposed design is a flexible RISC-V processor: AsteRISC. The originality of this core is to have optional registers at key points of its datapath, allowing the designer to have direct control over the critical path, in order to find the optimal one for the application. The chosen register configuration is selected through parameters before logic synthesis. Two architectural approaches are being explored: a non-pipelined approach, aimed at ensuring limited resource usage and offering a wide variety of different microarchitectures, and a flexible pipelined approach to extend the design space to architectures with higher performance capabilities.
A flexible System-On-Chip (SoC) framework is proposed, featuring, a multi-target approach. An architecture exploration environment is also presented, enabling the parallel search for maximum operating frequency for many micro-architectures and facilitating result interpretation.
Experimental results and analyses provide benchmarks, performance results on both FPGA devices and ASIC technologies. Results showcase the advantages of architectural flexibility to meet stringent performance demands. Indeed, they clearly demonstrate that each configuration exhibits distinct characteristics based on the targeted technology and the application context.
The study is anchored in the development of a SoC for a radar aiming function, utilizing the proposed processor to address the challenge of processing data within tight timing constraints, while keeping a low hardware footprint. Implementation results, down the layout, demonstrate that it is possible to offer the same functionalities as the original fixed architecture while allowing dynamic modification of its behavior by changing the software. The impacts, especially in terms of used surface area, are presented, allowing for a nuanced understanding of the underlying trade-offs.