Thesis defense of Denis FLORES - November 28th, 2023

Denis FLORES will defend his thesis on November 28th, 2023 at 10:00 am, (amphi JP. DOM – IMS Laboratory) on the subject : “Bit-Rate-Multiplier (BRM)-based Dithering-less Fractional Phase-Locked Loop for Ultra-low-power IoT Applications in 28-nm FD-SOI CMOS Technology”.

Through nowadays increase of Internet-of-Things (IoT) devices incorporated into the daily life applications, it came up the need of its optimal power efficiency to extend their battery life. One of the most power demanding components of the Radio Frequency (RF) transceiver is the frequency synthesis unit, therefore, its power optimization is highly desired.
This work presents the Bit-Rate-Multiplier (BRM)-based Fractional-N PLL, which settles a new approach for ultra-low-power (ULP) frequency synthesizers for IoT applications. The proposed architecture revisits an interesting concept of the late 60s called the Bit-Rate-Multiplier (BRM) and proposes an enhanced reduced complexity circuit based on this principle to perform a direct fractional division in the PLL. Thus, avoiding any use of a Sigma-Delta-Modulator while preserving good performance, energy efficiency and high bandwidth.

A 2.4-GHz IoT prototype was designed and fabricated in 28-nm FD-SOI CMOS technology from STMicroelectronics, thus performing the proof-of-concept of this architecture. The prototype operates at VDD=0.5V and achieves fractional and reference spur rejections of -39.5 and -49.2 dBc respectively without any calibration or compensation circuit. With a power consumption of 0.6mW, this architecture breaks the barrier of the sub-mW PLL proposals through an energy efficiency of 0.23 mW/GHz, keeping compliance with the Bluetooth Low Energy (BLE) Standard, and representing an attractive ULP frequency synthesis solution for IoT. Furthermore, the proposed solution employs a ring-oscillator which allows to keep compactness, resulting in a solution of only 0.0059 mm2 on its core area.