The D-band [110 GHz -170 GHz] is considered for very high-speed communications and the future deployment of 6G. Several technologies, such as III-V or silicon, can be considered. The main advantages of silicon are based on its high integration density and low cost. Therefore, the performances of these technologies have to be assessed in the context of 6G applications. The Power Amplifier is one of the key elements of the Radio-Frequency Front-End. Thus, the 28nm FD-SOI CMOS technology is of great interest due to its high maximum oscillation frequency and good power handling. This work presents the research results related to the design of power amplifiers in 28-nm FD-SOI CMOS technology for the D-band. This thesis explores various gain enhancement methods used in Power Amplifier architectures. Also, it examines power combiner architectures to address the two main challenges in the design of power ampli- fiers for the D-band. The design methods leading to these architectures and the measurement results are presented.
