Article (2)
Development of a high accuracy and stability test bench for ageing measurement of 16 nm FinFETs based FPGA Auteur(s): Justin Sobas, Tudor-Bogdan Airimitoaie, François Marc Année de publication: 2024 Journal: Microelectronics Reliability DOI: 10.1016/j.microrel.2022.114698 Lien HAL: https://hal.science/hal-04017664v1 A physical and versatile aging compact model for hot carrier degradation in SiGe HBTs under dynamic operating conditions Auteur(s): C. Mukherjee, F. Marc, M. Couret, G.G. Fischer, M. Jaoul, D. Céli, K. Aufinger, T. Zimmer, C. Maneux Année de publication: 2021 Journal: Solid-State Electronics DOI: 10.1016/j.sse.2019.107635 Lien HAL: https://hal.science/hal-02475429v1Conference proceedings (3)
Comparison of semi empirical modelling of FinFET FPGA ageing based on high stress short time with 20000 hours low stress measures Auteur(s): Justin Sobas, François Marc Année de publication: 2025 Journal: DOI: Lien HAL: https://hal.science/hal-05323090v1 Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors Auteur(s): Lucas Réveil, Mukherjee Chhandak, Cristell Maneux, Marina Deng, François Marc, Abhishek Kumar, Guilhem Larrieu, Arnaud Poittevin, Ian O'Connor, Oskar Baumgartner, David Pirker Année de publication: 2022 Journal: DOI: 10.1109/VLSI-SoC54400.2022.9939576 Lien HAL: https://hal.science/hal-03765079v1 3D logic cells design and results based on Vertical NWFET technology including tied compact model Auteur(s): Mukherjee Chhandak, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Cédric Marchand, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu Année de publication: 2021 Journal: DOI: 10.1109/VLSI-SOC46417.2020.9344094 Lien HAL: https://hal.science/hal-03166674v1Send a email to François MARC :
