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Soutenance de thèse Romane DUMONT - 29 mars 2022

Romane DUMONT soutiendra sa thèse mardi 29 mars à 10h, dans l'Amphi JP.DOM du Laboratoire IMS, sur le sujet suivant : "30 GHz frequency synthesis solutions in 65-nm PD-SOI technology".


As cellular communication now enters its fifth-generation (5G), millimeter-wave (mm- W) frequencies are supported for the first time. It has been an uncharted territory for the 3rd Generation Partnership Project (3GPP). Compared to 4G Long-Term Evolution (LTE), mobile user experiences are widely enhanced: the increase of data rates and connection densities while reducing the latency; and new opportunities are created in the development of new technologies (machine type communications for instance). 5G standards use both sub-6-GHz and mm-W frequency bands with wider channel bandwidth, multiple-input, multiple-output (MIMO) techniques, and complex modulations such as the 256 quadrature amplitude modulation (QAM). These specifications are known to impose stringent phase noise and spurious tone performances on the local oscillator (LO). That is why, 3GPP has especially paid great attention to mm-W local oscillator (LO) generation. In addition, as it is a mass-market application, the demand is growing to provide 5G mobile communications for everyone. Hence, it requires using a cost-optimized, high performance, and huge scale integration (VLSI) technology, such as the 65-nm CMOS PD-SOI technology from STMicroelectronics used in this thesis.

In this context, this dissertation proposes a solution for mm-W frequency generation in CMOS technology: the quadrature-coupled differentially injection-locked digitally controlled oscillator (QILDCO). The work presented in this dissertation presents the 5G standards specifications and the analysis of the state-of-the-art and its limitations, the detailed mm-W design methodology, and the design of technological demonstrators. The QILDCO implemented in 65-nm CMOS PD-SOI technology from STMicroelectronics demonstrates the feasibility of a mm-W frequency generation with a wide tuning range, low-jitter, and phase error performances while providing a very compact design. The design robustness is also validated. This design approach is not limited to 5G communications

and can be easily extended to other frequencies and other applications.

PLL bis

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