Nanostructure Devices for Logic and Memory and Beyond

Invited Paper

Sandip Tiwari

Cornell University

Ithaca, NY 14853, USA

st222@cornell.edu

Abstract—After six decades of device size reduction and its efficient use through hierarchical design, the semiconductor area encounters two major conflicting currents: (a) quantum, stochastic (atomic and signal/noise) and other probabilistic effects with size reduction at the bottom and (b) thermodynamic consequences in the inefficiencies of the information engine as a large numbers of devices are assembled together hierarchically at the top. This is the central intellectual challenge when discussing the future of nanostructure devices and their use in information machines. We discuss the conceptual fundamentals of the small and the large that ties this scale change that exists in time, size, energy, and other dimensions of the machinery. From this, we derive ideas for devices, robustness, information efficiency, and performance under practical constraints so that the next six decades are just as fruitful and useful for the society.